DDC Reference Sample Code : mti_irig_demo   Download 

This sample demonstrates using IRIG-B time code to synchronize multiple Chapter 10 Bus Monitors. It is a companion sample code for application note AN0008.

1. Overview

• On DDC hardware that support IRIG-B Digital/PWM input, this sample sets up a CH10 Bus Monitor to use external IRIG-B time for timestamping.
• It enables CH10 time packets, in addition to CH10 data packets. Time packets then arrive periodically every second. If no IRIG-B signal is detected, internal clock is used for time packets.
• For every CH10 data packet, it combines the absolute IRIG-B time received in time packets with the Relative Time Counter value of the CH10 data packets to generate time that is synchronised to the IRIG-B source.
• If the DDC hardware supports it, it provides the user with an option to generate IRIG-B traffic as well. This may be used as the IRIG-B source in the setup.
• It prints the messages monitored on the bus along with their absolute timestamp that is synced to the IRIG-B source.
• To test this sample, at least two DDC 1553 cards that are capable of IRIG-B input are needed and one IRIG-B time source.

2. APIs Demonstrated

• aceInitialize
• aceGetHwVersionInfo
• aceGetIRIGTx
• aceSetIRIGTx
• aceSetTimeTagRes
• aceMTIConfigure
• aceMTISetCh10TimePktId
• aceMTIStart
• aceMTICh10TimePktEnable
• aceMTIStop
• aceFree
• aceMTIGetCh10DataPkt
• aceMTIGetCh10TimePkt
• aceMTIFreeCh10TimePkt
• aceMTIFreeCh10DataPkt

3. Build and Test Details

The sample was built and tested using Visual Studio 2022 on on Windows 11 and using "make" on Fedora 35 Linux. BU-69092S0-110 v4.9.5 was used with BU-67110i on one computer and BU-67210i on another. Application note AN0008 describes the hardware setup needed to test this sample.